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general description the max8775 is a dual, step-down, interleaved, fixed- frequency, switch-mode power-supply (smps) con- troller with synchronous rectification. it is intended for gpu cores and i/o power generation in battery-pow- ered systems. flexible configuration allows the max8775 to operate as two independent single-phase regulators, or as one high-current two-phase regulator. configured in separate mode, the max8775 provides power to two dynamic voltage rails, one for the gpu core and the other for the i/o power rail. configured in combined mode, the max8775 functions as a two- phase, high-current, single-output gpu core regulator, powering the high-performance gpu engines used in gaming machines and media center notebooks. the refin voltage setting allows for multiple dynamic output voltages required by the different gpu operating and sleep states. automatic fault blanking, forced-pwm operation, and transition control are achieved by detecting the voltage change at refin. fixed-frequen- cy operation with 180 out-of-phase interleaving mini- mizes input ripple current from the lowest input voltages up to the 26v maximum input. current-mode control allows the use of low-esr output capacitors. internal integrators maintain high output accuracy over the full line-and-load range, in both forced-pwm mode and pulse-skipping mode. true differential current sensing provides accurate output current limit and cur- rent balance when operated in combined mode. independent on/off and skip control allows flexible power sequencing and power management. voltage- controlled soft-start reduces inrush current. soft-stop gradually ramps the output voltage down, preventing negative voltage dips. applications 2 to 4 li+ cells battery-powered devices media center and gaming notebooks gpu and i/o power supplies tracking output power supplies features dual-output, fixed-frequency, current-mode control combinable output for higher currents dynamic output voltages with automatic fault blanking and transition control true out-of-phase operation true differential current sense for accurate current limit and current balance 4v to 26v input range 100khz to 600khz switching frequency 0.5v to 2.5v adjustable outputs internal integrator for high output accuracy stable with low-esr output capacitors independent selectable pwm and skip-mode operation independent power-good outputs soft-start and soft-stop 2.5v precision reference < 1? typical shutdown current max8775 dual and combinable graphics core controller for notebook computers ________________________________________________________________ maxim integrated products 1 max8775 thin qfn 5mm x 5mm top view 29 30 28 27 12 11 13 osc v cc agnd ref refin2 14 ovp1 lx1 v dd pgnd bst1 dl2 lx2 12 csh1 4567 23 24 22 20 19 18 skip1 pgood1 csl2 csh2 pgood2 refin1 dl1 3 21 31 10 dtrans cci2 32 9 slew1 slew2 csl1 26 15 on2 on1 25 16 dh2 ovp2 bst2 8 17 dh1 skip2 pin configuration ordering information 19-0670; rev 0; 11/06 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. evaluation kit available part temp range pin- package pkg code max8775etj+ -40? to +85? 32 thin qfn 5mm x 5mm t3255-5 + denotes lead-free package.
max8775 dual and combinable graphics core controller for notebook computers 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (circuit of figure 1, v in = 12v, skip_ = pgnd = agnd, on_ = v cc = 5v, separate mode, t a = 0? to +85? , unless otherwise noted. typical values are at t a = +25?.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v dd, v cc , csh_, csl_ to agnd............................-0.3v to +6v on_, skip_ , pgood_ to agnd ..............................-0.3v to +6v ovp_, refin_ to agnd ...........................................-0.3v to +6v dtrans to agnd ....................................................-0.3v to +6v ref, osc, slew_, cci2 to agnd ...........-0.3v to (v cc + 0.3v) bst1, bst2 to agnd .............................................-0.3v to +36v lx1 to bst1..............................................................-6v to +0.3v lx2 to bst2..............................................................-6v to +0.3v dh1 to lx1 ..............................................-0.3v to (v bst 1 + 0.3v) dh2 to lx2 ..............................................-0.3v to (v bst2 + 0.3v) dl1, dl2 to pgnd .....................................-0.3v to (v dd + 0.3v) agnd to pgnd .....................................................-0.3v to +0.3v ref short circuit to agnd.........................................continuous ref current ......................................................................+10ma continuous power dissipation (t a = +70?) 32-pin, 5mm x 5mm, thin qfn (derate 21.3mw/? above +70?) .............................1702mw operating temperature range ...........................-40? to +85? junction temperature ......................................................+150? storage temperature range .............................-65? to +150? lead temperature (soldering, 10s) .................................+300? parameter sym b o l conditions min typ max units input supplies v in 426 input voltage range v bias v cc , v dd 4.5 5.5 v v cc undervoltage lockout threshold v uvlo rising edge, 50mv typical hysteresis 4.1 4.25 4.5 v quiescent supply current (v cc )i cc csl_ forced above their regulation points 1.5 2.5 ma quiescent supply current (v dd )i dd csl_ forced above their regulation points, skip mode < 1 5 ? shutdown supply current (v cc )i c c ( s h d n ) on1 = on2 = gnd < 1 5 ? shutdown supply current (v dd )i d d ( s h d n ) on1 = on2 = gnd < 1 5 ? smps controllers output voltage accuracy v refin_ - v csl_ with respect to refin_, refin_ = 0.5v to 2.5v, skip_ = v cc or gnd (note 1) -5 0 +5 mv output voltage-adjust range v csl_ either smps (note 2) 0.5 2.5 v re fin op er ati ng v ol tag e- ad j ust rang ev refin_ either smps (note 2) 0.5 2.5 v refinok threshold either smps 0.1 v refin transient detection threshold 5mv (typ) hysteresis ?5 mv combined-mode enabled threshold v refin2 3 v cc - 1 v cc - 0.4 v dc load regulation either smps, skip_ = v cc , zero to full load -0.1 % line regulation error either smps, 4v < v in < 26v 0.03 %/v r osc = 143k (f osc = 300khz nominal) -10 +10 switching-frequency accuracy (note 3) f osc r osc = 71.5k (f osc = 600khz nominal) to 432k (f osc = 99khz nominal) -15 +15 % maximum duty factor d max 91 93 % minimum on-time t onmin (note 4) 150 ns
max8775 dual and combinable graphics core controller for notebook computers _______________________________________________________________________________________ 3 electrical characteristics (continued) (circuit of figure 1, v in = 12v, skip_ = pgnd = agnd, on_ = v cc = 5v, separate mode, t a = 0? to +85? , unless otherwise noted. typical values are at t a = +25?.) parameter symbol conditions min typ max units 50 % smps1 to smps2 phase shift smps2 starts after smps1 180 deg i slew_ during transition 4.0 4.75 5.5 slew-rate current i slewss_ startup and shutdown 0.70 0.95 1.20 ? current limit current-limit threshold v limit v csh _ - v csl _ 26 30 34 mv current-limit threshold (negative) v neg v csh _ - v csl _ , skip_ = v cc -43 -36 -29 mv current-limit threshold (zero crossing) v zx v csh _ - v csl _ , skip_ = gnd 3 mv idle mode threshold i min v csh _ - v csl _ , skip_ = gnd 3.6 6 8.4 mv reference (ref) t a = +25? to +85? 2.482 2.50 2.518 reference voltage v ref v cc = 4.5v to 5.5v, i ref = 0 t a = 0? to +85? 2.475 2.50 2.525 v refer ence s our ce load reg ul ati on v ref i ref = 0? to 250? 0.25 1.5 mv reference sink load regulation i ref = -50? 6 mv ref lockout voltage v r e f ( u v l o ) rising edge, hysteresis = 100mv 2.3 v current balance current-balance amplifier (gmi) offset [v(csh1,csl1) - v(csh2,csl2)] at i cci = 0 -2 +2 mv current-balance amplifier (gmi) transconductance i cci / [v(csh1,csl1) - v(csh2,csl2)], v cci = v out = 0.5v to 2.5v, and v(csh_,csl_) = -60.0mv to +60.0mv 200 ? fault detection ovp_ adjust range v ovp_ 0.5 2.5 v outp ut over vol tag e tr i p thr eshol d rising edge measured at csl_, with respect to ovp_ set voltage 180 200 220 mv output overvoltage fault propagation delay t ovp 50mv overdrive 10 ? output undervoltage protection trip threshold falling edge measured at csl_, with respect to error comparator threshold -325 300 -275 mv output undevoltage fault propagation delay t uvp 50mv overdrive 10 ? output undervoltage protection blanking time t blank from rising edge of on_ 6144 1/f sw pgood_ lower trip threshold falling edge measured at csl_, with respect to error comparator threshold, hysteresis = 1% -180 -150 -120 mv pgood_ propagation delay t pgood _ falling edge, 50mv overdrive 10 ? idle mode is a trademark of maxim integrated products, inc.
max8775 dual and combinable graphics core controller for notebook computers 4 _______________________________________________________________________________________ electrical characteristics (continued) (circuit of figure 1, v in = 12v, skip_ = pgnd = agnd, on_ = v cc = 5v, separate mode, t a = 0? to +85? , unless otherwise noted. typical values are at t a = +25?.) parameter symbol conditions min typ max units pgood_ output low voltage i sink = 4ma 0.4 v pgood_ leakage current i pgood _ high state, pgood_ forced to 5.5v 1 a pgood_ transition blanking time measured from the time csl_ reaches the target voltage based on the slew rate set by c slew_ 20 ? lower threshold, 0.84v ref 2.0 2.2 current-balance fault comparator thresholds v(cci2, ref), 0.5v v fb 2.5v upper threshold, 1.2v ref 2.9 3.0 v thermal-shutdown threshold t shdn hysteresis = 15? +160 ? gate drivers dh_ gate driver on-resistance r dh bst_ - lx_ forced to 5v (note 5) 1.5 5 dl_, high state 1.7 5 dl_ gate driver on-resistance (note 5) r dl dl_, low state 0.6 3 dh_ gate driver source/ sink current i dh dh_ forced to 2.5v, bst_ - lx_ forced to 5v 2 a dl_ gate driver source current i dl ( source ) dl_ forced to 2.5v 1.7 a dl_ gate driver sink current i dl ( sink ) dl_ forced to 2.5v 3.3 a dl_ to dh_ 15 35 dead time t dead dh_ to dl_ 10 26 ns internal boost diode switch r on measure with 10ma of current 6.5 9 lx_, bst_ leakage current v bst _ = v lx _ = 28v < 2 20 a inputs and outputs logic input current on1, on2, dtrans , skip1 , skip2 -1 +1 ? logic input-high threshold on1, on2, dtrans , skip1 , skip2, hysteresis = 225mv 1.2 1.7 2.2 v input leakage current csh_, csl_, 0v, or v dd -0.15 +0.15 ?
max8775 dual and combinable graphics core controller for notebook computers _______________________________________________________________________________________ 5 electrical characteristics (circuit of figure 1, v in = 12v, skip_ = 0, on_ = v cc = 5v, separate mode, t a = -40? to +85? , unless otherwise noted.) (note 6) parameter symbol conditions min typ max units input supplies v in 426 input voltage range v bias v cc , v dd 4.5 5.5 v v cc undervoltage lockout v uvlo rising edge, 200mv typical hysteresis 4.1 4.5 v quiescent supply current (v cc )i cc csl_ forced above their regulation points 2.5 ma quiescent supply current (v dd )i dd csl_ forced above their regulation points 5 a shutdown supply current (v cc ) on1 = on2 = gnd 5 a shutdown supply current (v dd ) on1 = on2 = gnd 5 a main smps controllers pwm_ output voltage v refin_ - v csl_ with respect to refin_, refin_ = 0.5v to 2.5v, skip_ = v cc or gnd (note 1) -7.5 +7.5 mv output voltage adjust range v csl_ either smps (note 2) 0.5 2.5 v refin operating voltage adjust range v refin_ either smps (note 2) 0.5 2.5 v combined mode enabled v refin2 3v r osc = 143k (f osc = 300khz nominal) -15 +15 switching frequency accuracy (note 2) f osc r osc = 71.5k (f osc = 600khz nominal) to 432k (f osc = 99khz nominal) -20 +20 % maximum duty factor d max 90 % i slew_ during transition 3.75 5.50 slew-rate current i slewss_ startup and shutdown 0.7 1.2 ? current limit current-limit threshold v limit v csh _ - v csl _2535mv reference (ref) reference voltage v ref v cc = 4.5v to 5.5v, i ref = 0 2.462 2.538 v refer ence s our ce load reg ul ati on v ref i ref = 0? to 250? 2 mv reference sink load regulation i ref = -50? 10 mv current balance current-balance amplifier (gmi) offset [v(csh1,csl1) - v(csh2,csl2)] at i cci = 0 -3 +3 mv
max8775 dual and combinable graphics core controller for notebook computers 6 _______________________________________________________________________________________ note 1: when the inductor is in continuous conduction, the output voltage has a dc regulation level lower than the error comparator threshold by 50% of the ripple. in discontinuous conduction, the output voltage has a dc regulation level higher than the error comparator threshold by 50% of the ripple. note 2: operation below 0.5v but above the refok threshold is allowed, but the accuracy is not guaranteed. note 3: the max8775 cannot operate over all combinations of frequency, input voltage (v in ), and output voltage. for large input-to- output differentials and high switching-frequency settings, the required on-time might be too short to maintain the regulation specifications. under these conditions, a lower operating frequency must be selected. the minimum on-time must be greater than 150ns, regardless of the selected switching frequency. on-time and off-time specifications are measured from the 50% point to the 50% point at the dh_ pin with lx_ = gnd, vbst_ = 5v, and a 250pf capacitor connected from dh_ to lx_. actual in-circuit times may differ due to mosfet switching speeds. note 4: specifications are guaranteed by design, not production tested. note 5: production testing limitations due to package handling require relaxed maximum on-resistance specifications for the thin qfn package. note 6: specifications to t a = -40? to +85? are guaranteed by design, not production tested. electrical characteristics (continued) (circuit of figure 1, v in = 12v, skip_ = 0, on_ = v cc = 5v, separate mode, t a = -40? to +85? , unless otherwise noted.) (note 6) parameter symbol conditions min typ max units fault detection ovp_ adjust range v ovp_ 0.5 2.5 v o utp ut o ver vol tag e tr i p thr eshol d rising edge measured at csl_, with respect to ovp_ set voltage 180 220 mv output undervoltage protection trip threshold falling edge measured at csl_, with respect to error comparator threshold 275 325 mv pgood_ lower trip threshold falling edge measured at csl_ with respect to error comparator threshold, hysteresis = 1% -180 -120 mv pgood_ output low voltage i sink = 4ma 0.4 v lower threshold, 0.84v ref 2.0 2.2 current-balance fault comparator thresholds v(cci2, ref), 0.5v v fb 2.5v upper threshold, 1.2v ref 2.9 3.1 mv gate drivers dh_ gate driver on-resistance r dh bst_ - lx_ forced to 5v (note 4) 5 dl_, high state 5 dl_ gate driver on-resistance (note 4) r dl dl_, low state 3 inputs and outputs logic input-high threshold on1, on2, dtrans , skip1 , skip2 , hysteresis = 225mv 1.2 2.2 v
max8775 dual and combinable graphics core controller for notebook computers _______________________________________________________________________________________ 7 1-phase efficiency vs. load current (v out = 1.5v) max8775 toc01 load current (a) efficiency (%) 10 1 50 60 70 80 90 100 40 0.1 100 v in = 7v, pwm v in = 12v, pwm v in = 20v, pwm v in = 7v, skip v in = 12v, skip v in = 20v, skip 2-phase efficiency vs. load current (v out = 1.5v) max8775 toc02 load current (a) efficiency (%) 10 1 50 60 70 80 90 100 40 0.1 100 v in = 7v, pwm v in = 12v, pwm v in = 20v, pwm v in = 7v, skip v in = 12v, skip v in = 20v, skip efficiency vs. load current (v out = 1.5v) max8775 toc03 load current (a) efficiency (%) 10 1 50 60 70 80 90 100 40 0.1 100 1-phase, pwm v in = 12v v out = 1.5v 2-phase, pwm 1-phase, skip 2-phase, skip output voltage vs. load current max8775 toc04 load current (a) output voltage (v) 20 25 10 15 5 1.497 1.499 1.501 1.503 1.505 1.495 030 pwm mode skip mode v in = 12v v out = 1.5v efficiency vs. load current (v out = 1.2v) max8775 toc05 load current (a) efficiency (%) 10 1 50 60 70 80 90 100 40 0.1 100 1-phase, pwm v in = 12v v out = 1.2v 2-phase, pwm 1-phase, skip 2-phase, skip no-load supply current vs. input voltage (skip mode) max8775 toc06 input voltage (v) supply current (ma) 16 20 812 4 0.01 0.1 1 10 0.001 024 i cc i dd i in no-load supply current vs. input voltage (1-phase pwm mode) max8775 toc07 input voltage (v) supply current (ma) 16 20 812 4 10 100 1 024 i cc i dd i in no-load supply current vs. input voltage (2-phase pwm mode) max8775 toc08 input voltage (v) supply current (ma) 16 20 812 4 10 100 1 024 i cc i dd i in current-sense offset vs. load current (2-phase pwm mode) max8775 toc09 load current (a) current balance offset (mv) 20 25 10 15 5 0 -0.5 0.5 1.0 -1.0 030 typical operating characteristics (circuit of figure 1, v in = 12v, v dd = v cc = 5v, skip_ = gnd, t a = +25?, unless otherwise noted.)
max8775 dual and combinable graphics core controller for notebook computers 8 _______________________________________________________________________________________ typical operating characteristics (continued) (circuit of figure 1, v in = 12v, v dd = v cc = 5v, skip_ = gnd, t a = +25?, unless otherwise noted.) startup waveforms max8775 toc10 0 0 5a 200 s/div 0 0 a b d c e 0 d: pgood1, 5v/div e: i lx1 , 5a/div a: on1, 5v/div b: dl1, 5v/div c: v out1 , 1v/div skip1 = gnd, r load1 = 1 , v in = 12v shutdown waveforms max8775 toc11 0 1.5v 0 5a 0 0 a b d c e 0 d: pgood1, 5v/div e: i lx1 , 5a/div a: on1, 5v/div b: dl1, 5v/div c: v out1 , 1v/div skip1 = gnd, r load1 = 1 , v in = 12v 200 s/div startup/shutdown same slew rate 0 0 5v 5v 0 0 a b d c e 0 d: pgood1, 5v/div e: pgood2, 5v/div a: on1, on2, 5v/div b: v out1 , 1v/div c: v out2 , 1v/div c slew1 = c slew2 = 470pf r load1 = r load2 = 1 400 s/div max8775 toc12 startup/shutdown same start time max8775 toc13 0 0 5v 5v 0 400 s/div 0 a b d c e 0 d: pgood1, 5v/div e: pgood2, 5v/div a: on1, on2, 5v/div b: v out1 , 1v/div c: v out2 , 1v/div c slew1 = 470pf, c slew2 = 600pf r load1 = r load2 = 1 load transient (separate mode) max8775 toc14 0 10a 5v 0 20 s/div 1.2v 12v a b d c 0 c: lx1, 10v/div d: i lx1 , 10a/div a: v out1 , 100mv/div b: dl1, 5v/div v in = 12v, v out1 = 1.2v skip1 = gnd i out1 = 1a to 11a to 1a load transient (combined mode) max8775 toc15 0 10a 0 1.5v 12v 12v a b d c 0 c: lx1, 10v/div d: lx2, 10v/div a: v out1 , 100mv/div b: i lx1 , 10a/div v in = 12v, v out = 1.5v i out1 = 5a to 25a to 5a 20 s/div
max8775 dual and combinable graphics core controller for notebook computers _______________________________________________________________________________________ 9 typical operating characteristics (continued) (circuit of figure 1, v in = 12v, v dd = v cc = 5v, skip_ = gnd, t a = +25?, unless otherwise noted.) switching waveforms max8775 toc16 12v 12v 1.5v 1.2v 12v a b d e c 0 0 d: v out2 , 50mv/div e: v in , 50mv/div a: lx1, 10v/div b: lx2, 10v/div c: v out1 , 50mv/div v in = 12v, v out1 = 1.5v, v out2 = 1.2v i out1 = 5a, i out2 = 5a 2 s/div refin transition waveforms (dtrans = v cc ) max8775 toc17 12v 1.5v 1.5v 1.2v 1.2v 10a a b d c 0 0 c: v out1 , 200mv/div d: i lx1 , 10a/div a: refin1, 500mv/div b: lx1, 10a/div v in = 12v, v refin1 = 1.2v to 1.5v to 1.2v i out1 = 1a skip1 = gnd 100 s/div refin transition waveforms (dtrans = gnd) max8775 toc18 12v 1.5v 1.5v 1.2v 1.2v a b d c 0 0 c: v out1 , 200mv/div d: i lx1 , 10a/div a: refin1, 500mv/div b: lx1, 10a/div v in = 12v, v refin1 = 1.2v to 1.5v to 1.2v i out1 = 1a skip1 = gnd 40 s/div combined-mode phase transition max8775 toc19 12v 12v 1.2v a b d c 0 0 0 c: lx1, 10v/div d: lx2, 10v/div a: v out , 50mv/div b: on2, 5v/div v in = 12v, v out = 1.2v i out = 10a 10 s/div combined-mode phase transition max8775 toc20 10a 10a 1.2v a b d c 0 0 0 c: i lx2 , 10a/div d: i lx1 , 10a/div a: v out , 50mv/div b: on2, 5v/div v in = 12v, v out = 1.2v i out = 10a 10 s/div
max8775 dual and combinable graphics core controller for notebook computers 10 ______________________________________________________________________________________ pin description pin name function 1 ovp1 smps1 overvoltage adjust input. the overvoltage trip threshold for smps1 is 200mv above the voltage at ovp1. connect ovp1 to v cc to disable ovp for smps1. ovp1 sets the overvoltage threshold for both phases in combined mode. 2 osc oscillator adjustment input. connect a resistor (r osc ) between osc and agnd to set the switching frequency (per phase): f osc = 300khz x 143k / r osc a 71.5k to 432k corresponds to switching frequencies of 600khz to 100khz, respectively. ensure the minimum on-time requirement is met for the selected frequency. 3 refin1 smps1 external reference input. refin1 sets the output regulation voltage (v csl1 = v refin1 ). refin1 sets the output regulation voltage in combined mode (v csl1 = v csl2 = v refin1 ). 4v cc analog supply input. connect to the system supply voltage (+4.5v to +5.5v) through a series 10 resistor. bypass v cc to agnd with a 1? or greater ceramic capacitor. 5 agnd analog ground. connect backside pad to agnd. 6 ref 2.5v reference voltage output. bypass ref to agnd with a 0.1? or greater ceramic capacitor. the maximum value of this cap is 1?. the reference can source up to 250?. loading ref degrades output-voltage accuracy according to the ref load-regulation error (see typical operating characteristics ). the reference shuts down when both on1 and on2 are low. 7 refin2 smps2 external reference input. refin2 sets the feedback regulation voltage (v csl2 = v refin2 ). connect refin2 to v cc to select combined mode. see ovp2 pin connection below. 8 ovp2 smps2 overvoltage adjust input. the overvoltage trip threshold for smps2 is 200mv above the voltage at ovp2. connect ovp2 to v cc to disable ovp for smps2. connect ovp2 to ref in combined mode when ovp is enabled. connect ovp2 to v cc in combined mode when ovp is disabled. 9 slew2 smps2 slew-rate control. connect a capacitor from slew2 to agnd to set the smps2 slew rate: slew rate ( v out2 / t) = i slew2 / c slew2 during startup and shutdown, smps2 ramps at 1/5 the programmed slew rate. connect slew2 to slew1 in combined mode. 10 cci2 current-balance compensation for smps2. when combining smps1 and smps2, connect a 47pf capacitor between cci2 and agnd. leave cci2 open when operating smps1 and smps2 separately. 11 pgood2 smps2 open-drain power-good output. pgood2 is low when smps2 is more than 150mv below its regulation threshold, when a 0v fault occurs, during soft-start, and in shutdown. pgood2 is the current-balance fault indicator when operating in combined mode. 12 skip2 low-noise mode control for smps2. connect skip2 to gnd for normal idle mode (pulse-skipping) operation or to v cc for pwm mode (fixed frequency). skip2 is ignored in combined mode. 13 csh2 positive current-sense input for smps2. connect to the positive terminal of the current-sense element. figure 10 describes two different current-sensing options. 14 csl2 negative current-sense and feedback input for smps2. connect to the negative terminal of the current-sense element. csl2 regulates to refin2. figure 10 describes two different current-sensing options. csl2 regulates to refin1 in combined mode. 15 on2 smps2 enable input. drive on2 high to enable smps2. drive on2 low to shut down smps2. when both outputs are combined, on1 is the master control input to enable/disable the combined output, while on2 enables/disables phase 2, allowing 1- or 2-phase operation.
max8775 dual and combinable graphics core controller for notebook computers ______________________________________________________________________________________ 11 pin description (continued) pin name function 16 dh2 high-side gate-driver output for smps2. dh2 swings from lx2 to bst2. 17 bst2 boost flying-capacitor connection for smps2. connect to an external capacitor as shown in figure 1. an optional resistor in series with bst2 allows the dh2 turn-on current to be adjusted. 18 lx2 inductor connection for smps2. connect lx2 to the switched side of the inductor. lx2 is the lower supply rail for the dh2 high-side gate driver. 19 dl2 low-side gate-driver output for smps2. dl2 swings from pgnd to v dd. 20 pgnd power ground 21 v dd supply voltage input for the dl_ gate drivers. connect to a 5v supply. bypass v dd to agnd with a 1? or greater ceramic capacitor. 22 dl1 low-side gate-driver output for smps1. dl1 swings from pgnd to v dd . 23 lx1 inductor connection for smps1. connect lx1 to the switched side of the inductor. lx1 is the lower supply rail for the dh1 high-side gate driver. 24 bst1 boost flying-capacitor connection for smps1. connect to an external capacitor as shown in figure 1. an optional resistor in series with bst1 allows the dh1 turn-on current to be adjusted. 25 dh1 high-side gate-driver output for smps1. dh1 swings from lx1 to bst1. 26 on1 smps1 enable input. drive on1 high to enable smps1. drive on1 low to shut down smps1. when both outputs are combined, on1 is the master control signal to enable/disable the combined output, while on2 enables/disables phase 2, allowing 1- or 2-phase operation. 27 csl1 negative current-sense and feedback input for smps1. connect to the negative terminal of the current-sense element. csl1 regulates to refin1. figure 10 describes two different current-sensing options. 28 csh1 positive current-sense input for smps1. connect to the positive terminal of the current-sense element. figure 10 describes two different current-sensing options. 29 skip1 low-noise mode control for smps1. connect skip1 to gnd for normal idle mode (pulse-skipping) operation or to v cc for pwm mode (fixed frequency). when both outputs are combined, skip2 is ignored and skip1 sets the skip function for both smps1 and smps2. 30 p g oo d 1 smps1 open-drain power-good output. pgood1 is low when smps1 is more than 150mv below its regulation threshold, when a 0v fault occurs, during soft-start, and in shutdown. pgood1 is the voltage-regulation fault indicator when operating in combined mode. 31 dtrans forced-downward transient disable input. connect dtrans to v cc to disable the forced-downward transition detection feature when operating in pulse-skipping mode, allowing the output to fall at a rate determined by the load current and total output capacitance. connect dtrans to agnd to enable the forced downward-transition detection feature. 32 slew1 smps1 slew-rate control. connect a capacitor from slew1 to agnd to set the smps1 slew rate: slew rate ( v out1 / t) = i slew1 / c slew1 during startup and shutdown, smps1 ramps at 1/5 the programmed slew rate. in combined mode, the slew rate is set by both slew1 and slew2. connect slew1 and slew2 together in combined mode: combined slew rate ( v out / t) = (i slew1 + i slew2 ) / (c slew1 + c slew2 ) ep exposed backside pad. connect the exposed backside pad to agnd.
max8775 detailed description the max8775 is a dual fixed-frequency step-down con- troller for low-voltage i/o and graphics core (gpu) sup- plies. it can be configured as two separate regulators generating two independent outputs. alternatively, the max8775 can be configured in combined mode as a two-phase, single-output, high-current regulator, pow- ering the high-performance graphics cores used in game machines and media center notebooks. the standard applications circuit (figure 1) generates dynamically adjustable output voltages on both out- puts. refin voltage setting allows for multiple dynamic dual and combinable graphics core controller for notebook computers 12 ______________________________________________________________________________________ v dd v cc c4 1 f osc r osc 154k cci2 ref r7 10 pgood1 +5v r8 100k pgood2 gnd skip1 skip2 on1 on2 slew1 c ref 0.1 f slew2 not used dtrans c bst1 0.1 f +5v lx1 dh1 bst1 dl1 csl1 csh1 c3 2.2 f input v in 7v to 20v l1 0.88 h d l1 c in1 n h1 n l1 v out1 1.5v/1.2v 15a csl2 csh2 lx2 dh2 bst2 dl2 analog ground power ground r sense1 1.5m r10 150 r11 10 c1 2.2nf c2 4.7nf r1 100k ovp1 refin1 ref v out1(l) v out2(l) v out1(h) v out2(h) see table 1 for component specifications. r3 249k r2 150k ovp2 refin2 ref r9 100k c out1 (2) 330 f pgnd max8775 c slew1 470pf c slew2 470pf r4 100k r6 249k r5 150k c bst2 0.1 f input v in 7v to 20v l2 0.88 h d l2 c in2 n h2 n l2 v out2 1.5v/1.2v 15a r sense2 1.5m r12 150 r13 10 c5 2.2nf c6 4.7nf c out2 (2) 330 f ep figure 1. max8775 separate output typical operating circuit
output voltages required by the different gpu operating and sleep states. automatic fault blanking, forced-pwm operation, and transition control are achieved by detecting the voltage change at refin. the interleaved, fixed-frequency architecture provides 180 out-of-phase operation to reduce the input capaci- tance required to meet the rms input-current ratings. each controller consists of a multi-input pwm compara- tor, high-side and low-side gate drivers, fault protec- tion, power-good detection, soft-start, and shutdown logic. current-mode control allows the use of low-esr output capacitors. in combined mode (figure 2), phase 1 provides the main voltage-control loop while phase 2 maintains the max8775 dual and combinable graphics core controller for notebook computers ______________________________________________________________________________________ 13 v dd v cc c4 1 f osc r osc 154k cci2 ref r7 10 pgood1 +5v r8 100k pgood2 gnd skip1 skip2 on1 on2 slew1 c ref 0.1 f slew2 not used dtrans c bst1 0.1 f +5v lx1 dh1 bst1 dl1 csl1 csh1 c3 2.2 f input v in 7v to 20v l1 0.56 h d l1 c in1 n h1 n l1 v out 1.5v/1.2v 40a csl2 csh2 lx2 dh2 bst2 dl2 analog ground power ground r sense1 1.0m r10 100 r11 10 c1 2.2nf c2 4.7nf r1 100k ovp1 refin1 ref ref v cc v out(l) v out(h) connect refin2 to v cc and ovp2 to ref or v cc for combined-mode operation see table 1 for component specifications. r3 249k r2 150k ovp2 refin2 r9 100k c out (4) 330 f pgnd max8775 c slew 1000pf c bst2 0.1 f input v in 7v to 20v l2 0.56 h d l2 c in2 n h2 n l2 r sense2 1.0m r12 100 r13 10 c5 2.2nf c6 4.7nf c cci2 47pf ep figure 2. max8775 combined-output typical operating circuit
max8775 current balance. pgood1 indicates when the com- bined output is in regulation, while pgood2 indicates the currents in both phases are balanced. phase 2 can be enabled or disabled based on the load current required, maximizing efficiency over the full output cur- rent range. figure 3 is the max8775 functional block diagram. dual and combinable graphics core controller for notebook computers 14 ______________________________________________________________________________________ 2.5v ref ref smps 1 csl1 on1 pgood1 csh1 dl1 dh1 lx1 bst1 agnd v cc v dd skip1 v in refin1 dtrans ovp1 slew1 +5v bias osc smps 2 on2 csl2 csh2 dl2 dh2 lx2 bst2 skip2 pgood 2 ovp2 refin2 cci2 slew2 slope comp pgnd 4x refin power- good trans refin slew soft-start/ soft-stop ovp osc pwm driver block max8775 figure 3. max8775 functional block diagram
see table 1 for component selections and table 2 for the component manufacturers. smps 5v bias supply (v cc and v dd ) the max8775 smpss require a 5v bias supply in addi- tion to the high-power input supply (battery or ac adapter). v dd is the power rail for the mosfet gate drive, and v cc is the power rail for the ic. connect the external 4.5v to 5.5v supply directly to v dd and con- nect v dd to v cc through an rc filter, as shown in figure 1. the maximum supply current required is: i bias = i cc + f sw (q g(nl1) + q g1(nh1) +q g2(nl2) + q g2(nh2) ) = 1.8ma to 40ma where i cc is 1.8ma, f sw is the switching frequency, and q g_ is the mosfet data sheet? total gate-charge specification limits at v gs = 5v. reference (ref) the 2.5v reference is accurate to ?% over tempera- ture and load, making ref useful as a precision system reference. bypass ref to gnd with a 0.1? or greater ceramic capacitor. the reference sources up to 250? and sinks 50? to support external loads. max8775 dual and combinable graphics core controller for notebook computers ______________________________________________________________________________________ 15 component v in = 7v to 24v v out1 = 1.0v - 1.5v / 15a v in = 7v to 24v v out2 = 1.8v / 10a v in = 7v to 24v v out1 = 1.0v - 1.5v / 40a mode separate (figure 1) separate combined (figure 2) switching frequency 280khz 280khz 280khz c in_ , input capacitor (2) 10?, 25v taiyo yuden tmk432bj106km (1) 10?, 25v taiyo yuden tmk432bj106km (4) 10?, 25v taiyo yuden tmk432bj106km c out_ , output capacitor (2) 330?, 6.3v, 7m , low-esr capacitor panasonic eefsd0d331xr (1) 330?, 6.3v, 7m , low-esr capacitor panasonic eefsd0d331xr (4) 330?, 6.3v, 7m , low-esr capacitor panasonic eefsd0d331xr n h_ high-side mosfet (1) vishay/siliconix si7634dp (1) international rectifier irf7811w (1) vishay/siliconix si7634dp n l_ low-side mosfet (1) vishay/siliconix si7336adp (1) vishay/siliconix si7336adp (2) vishay/siliconix si7336adp d l_ schottky rectifier 3a, 40v schottky diode central semiconductor cmsh3-40 3a, 40v schottky diode central semiconductor cmsh3-40 3a, 40v schottky diode central semiconductor cmsh3-40 l_ inductor 0.88?, 18a, 2.1m nec/tokin mpc1040lr88 1.8?, 13.8a, 6.2m sumida cdep105(s)-1r8 0.56_h, 26a, 1.3m nec/tokin mpc1040lr56 panasonic etqp4lr56wfc current-sense r sense _ 1.5m , 1w, 2512 panasonic erjm1wtj1m5u 2m , 0.5w, 2010 vishay wsl20102l000f 1.0m , 1w, 2512 panasonic erjm1wtj1m0u table 1. component selection for standard applications supplier website supplier website avx www.avx.com panasonic www.panasonic.com/industrial central semiconductor www.centralsemi.com sanyo www.secc.co.jp coilcraft www.coilcraft.com sumida www.sumida.com coiltronics www.coiltronics.com taiyo yuden www.t-yuden.com fairchild semiconductor www.fairchildsemi.com tdk www.component.tdk.com international rectifier www.irf.com toko www.tokoam.com kemet www.kemet.com vishay (dale, siliconix) www.vishay.com table 2. component suppliers
max8775 smps detailed description smps enable controls (on1, on2) on1 and on2 provide independent control of output soft-start and soft-shutdown. this allows flexible control of startup and shutdown sequencing. the outputs may be started simultaneously, sequentially, or independent- ly. to provide sequential startup, connect on_ of one regulator to pgood_ of the other. for example, with on1 connected to pgood2, out1 soft-starts after out2 is in regulation. additionally, tracking and ratio- metric startup and shutdown can be achieved using the slew_ capacitors. see the startup sequencing section. when configured in combined mode (refin2 = v cc ), on1 is the master control input that enables/disables the combined output. on2 enables/disables only the 2nd phase, allowing dynamic switching between one- phase and two-phase operation. toggle on_ low to clear the overvoltage, undervoltage, and thermal-fault latches. soft-start and soft-shutdown soft-start begins when on_ is driven high and ref is in regulation. during soft-start, the output is ramped up from 0v to the final set voltage at 1/5 the slew rate pro- grammed by the capacitor at the slew_ pin. this reduces inrush current and provides a predictable ramp-up time for power sequencing: soft-start/stop slew rate ( v out_ / t) = i slewss_ / c slew_ where i slewss_ is 0.95? (typ), and c slew_ is the capacitor across the slew_ pin and agnd. a 470pf capacitor programs a slew rate of approximately 10mv/?, and a soft-start, soft-shutdown slew rate of approximately 2mv/?. soft-shutdown begins after on_ goes low, an output undervoltage fault, or a thermal fault. during soft-shut- down, the output is ramped down to 0v at 1/5 the pro- grammed slew rate, reducing negative inductor currents that can cause negative voltages on the out- put. at the end of soft-shutdown, dl_ is driven high until startup is again triggered by a rising edge of on_. the reference is turned off when both outputs have been shut down. when configured in separate mode, the two outputs are independent. a fault at one output does not trigger shutdown of the other. startup sequencing individually programmable slew-rate control, on/off con- trol, and power-good outputs allow flexible configuration of the max8775 for different power-up sequencing. this is useful in applications where one power rail needs to come up after another, track another rail, or reach regu- lation at about the same time. figures 4, 5, and 6 show three configurations for startup sequencing. fixed-frequency, current-mode pwm controller the heart of each current-mode pwm controller is a multi-input, open-loop comparator that sums three sig- nals: the output voltage-error signal with respect to the reference voltage, the current-sense signal, and the slope compensation ramp (figure 3). the max8775 uses a direct-summing configuration, approaching ideal cycle-to-cycle control over the output voltage dual and combinable graphics core controller for notebook computers 16 ______________________________________________________________________________________ ref refin2 pgood1 = on2 on1 refin1 v out1 v out2 pgood2 20 s delayed startup/shutdown timing ref refin2 refin1 agnd slew1 slew2 c slew1 = c slew2 c ref 1/5 programmed slew rate 1/5 programmed slew rate max8775 20 s figure 4. max8775 delayed startup/shutdown timing
without a traditional error amplifier and the phase shift associated with it. the max8775 uses a relatively low loop gain, allowing the use of lower cost output capacitors. the relative gain of the voltage comparator to the current compara- tor is internally fixed at 4:1. the high current gain results in stable operation even with low-output esr capacitors. an internal integrator corrects for any load- regulation error caused by the high current gain. the low value of loop gain helps reduce output filter capaci- tor size and cost by shifting the unity-gain crossover frequency to a lower level. frequency selection (fsel) the osc input programs the pwm mode switching fre- quency. connect a resistor (r osc ) between osc and agnd to set the switching frequency (per phase): f sw = 300khz x 143k / r osc r osc values between 71.5k and 432k correspond to switching frequencies of 600khz to 100khz, respectively. high-frequency (600khz) operation optimizes the appli- cation for the smallest component size, trading off effi- ciency due to higher switching losses. this may be acceptable in ultra-portable devices where the load currents are lower. low-frequency (100khz) operation offers the best overall efficiency at the expense of com- ponent size and board space. max8775 dual and combinable graphics core controller for notebook computers ______________________________________________________________________________________ 17 ref refin1 pgood1 on1 = on2 refin2 v out2 v out1 pgood2 20 s 20 s tracking startup/shutdown timing ref refin1 refin2 agnd slew1 slew2 c slew1 = c slew2 1/5 programmed slew rate 1/5 programmed slew rate max8775 c ref figure 5. max8775 tracking startup/shutdown timing ref refin1 pgood1 on1 = on2 refin2 v out2 v out1 pgood2 20 s ratiometric startup/shutdown timing ref refin1 refin2 agnd slew1 slew2 c slew1 > c slew2 1/5 programmed slew rate 1/5 programmed slew rate max8775 c ref figure 6. max8775 ratiometric startup/shutdown timing
max8775 when selecting a switching frequency, the minimum on- time at the highest input voltage and lowest output voltage must be greater than the 150ns (max) minimum on-time specification in the electrical characteristics table: v out(min) / v in(max) x t sw > t on(min) a good rule is to choose a minimum on-time of at least 200ns. when in pulse-skipping operation skip_ = gnd, the minimum on-time must take into consideration the time needed for proper skip-mode operation. the on-time for a skip pulse must be greater than the 150ns (max) minimum on-time specification in the electrical characteristics table: forced-pwm mode to maintain low-noise, fixed-frequency operation, drive skip_ high to put the output into forced-pwm mode. this disables the zero crossing comparator and allows negative inductor current. during forced-pwm mode, the switching frequency remains constant and the no- load supply current is typically between 20ma and 40ma per phase, depending on external mosfets and switching frequency. light-load operation control ( skip_ ) the max8775 includes skip_ inputs, which enable the corresponding outputs to operate in discontinuous mode. connect skip_ to gnd to enable the zero-cross- ing comparators of either controller. when the zero- crossing comparator is enabled, the controller forces dl_ low when the current-sense inputs detect zero inductor current. this keeps the inductor from discharg- ing the output capacitors and forces the controller to skip pulses under light-load conditions to avoid over- charging the output. during skip mode, the v dd current consumption is reduced and efficiency is improved. in combined mode, skip2 is unused, and skip1 sets the operating mode for both phases. at very light loads, one- phase and two-phase pulse-skipping operation have about the same efficiency (see the efficiency vs. load current (v out =1.5v) graph in typical operating characteristics ). keeping the max8775 in two-phase skip allows it to dynamically respond to a full-load transient without requiring any system level-control signal to indi- cate the state of the gpu core. idle mode current-sense threshold when pulse-skipping mode is enabled, the on-time of the step-down controller terminates when the output voltage exceeds the feedback threshold and when the current-sense voltage exceeds the idle mode current- sense threshold. under light-load conditions, the on- time duration depends solely on the idle mode current-sense threshold, which is 20% ( skip_ = gnd) of the full load current-limit threshold. this forces the controller to source a minimum amount of power with each cycle. to avoid overcharging the output, another on-time cannot begin until the output voltage drops below the feedback threshold. since the zero-crossing comparator prevents the switching regulator from sink- ing current, the controller must skip pulses. therefore, the controller regulates the valley of the output ripple under light-load conditions. automatic pulse-skipping crossover in skip mode, an inherent automatic switchover to pfm takes place at light loads (figure 7). this switchover is affected by a comparator that truncates the low-side switch on-time at the inductor current? zero crossing. the zero-crossing comparator senses the inductor cur- rent across csh_ and csl_. once v csh_ - v csl _ drops below the 3mv zero-crossing, current-sense threshold, the comparator forces dl_ low. this mechanism causes the threshold between pulse-skipping pfm and nonskip- ping pwm operation to coincide with the boundary between continuous and discontinuous inductor-current operation (also known as the ?ritical-conduction?point). the load-current level at which pfm/pwm crossover occurs, i load(skip) , is determined by: i vv v lv f load skip in out out in osc () () = ? 2 lv rvv t imin sense i n max out min on min ? () () () () dual and combinable graphics core controller for notebook computers 18 ______________________________________________________________________________________ t on(skip) = v out v in f osc inductor current i load(skip) 2 i load = i load(skip) time on-time 0 figure 7. pulse-skipping/discontinuous crossover point
in combined-mode operation, since the load is shared between two phases, the load current at which pfm/pwm crossover occurs is twice that of each phase? crossover current. the switching waveforms may appear noisy and asyn- chronous when light loading causes pulse-skipping operation, but this is a normal operating condition that results in high light-load efficiency. trade-offs in pfm noise vs. light-load efficiency are made by varying the inductance. generally, low inductance produces a broader efficiency vs. load curve, while higher values result in higher full-load efficiency (assuming that the coil resistance remains fixed) and less output voltage ripple. penalties for using higher inductor values include larger physical size and degraded load-tran- sient response (especially at low input-voltage levels). output voltage the max8775 regulates each output to the voltage set at refin_ by sensing the csl_ pin. changing the volt- age at refin_ allows the max8775 to be used in appli- cations that require dynamic output voltage changes between two or more set points. figure 1 shows a dynamically adjustable resistive voltage-divider net- work at refin_. using system control signals to drive the gate(s) of small-signal mosfets, resistors can be switched in and out of the refin_ resistor-divider, dynamically changing the voltage at refin_. the main output voltage is determined by the following equation: where r eq is the equivalent resistance between refin_ and ground, and r top is the resistance between refin_ and ref (see figures 1 and 2). in combined mode (refin2 = v cc ), refin1 sets the voltage of the combined output. internal integrator the max8775 includes an internal transconductance amplifier that integrates the feedback voltage and pro- vides fine adjustment to the regulation voltage, allowing accurate dc output-voltage regulation regardless of the output ripple voltage. when the inductor conducts continuously, the max8775 regulates the peak of the output ripple. the internal integrator corrects for errors due to esr ripple voltage, slope compensation, and current-sense load regulation, maintaining high dc accuracy throughout the full load range, including light- load operation while in pulse-skipping mode. dynamic output voltages the max8775 controller automatically detects upward transitions of 25mv at refin_, enters forced-pwm operation, and blanks the power-good thresholds until 20? after the output reaches the new regulation target. the max8775 slews the output up at a rate set by the slew capacitor c slew _: slew rate ( v out_ / t) = i slew_ / c slew_ where i slew_ is 4.75? (typ), and c slew_ is the capacitor across the slew_ pin and agnd. a 470pf capacitor programs a slew rate of approximately 10mv/?. setting dtrans low enables the automatic refin_ detection downward transitions (figure 8). this feature is especially useful as it allows the max8775 to be set in the high-efficiency, pulse-skipping operation ( skip_ = low), while voltage transitions are automatically taken care of by the max8775. forced downward transitions return the energy from the output capacitors back to the input reservoir. vv r rr out pwm ref eq eq top () = + ? ? ? ? ? ? max8775 dual and combinable graphics core controller for notebook computers ______________________________________________________________________________________ 19 v out(high) v out v out(low) pgood threshold ov threshold refin mode refin(high) refin(low) tracking ov 20 s 20 s forced-pwm forced-pwm dh pulse skip pulse skip pulse skip pgood blank high-z blank high-z figure 8. refin transition (skip mode, downward transition enabled)
max8775 setting dtrans high disables the forced downward refin_ transition. this allows the output voltage to drift down at a rate determined by the load current and the total output capacitance (figure 9). downward transitions in some systems are less critical from a timing standpoint because the voltage is above the new lower target. the power consumed in moving the output voltage to the new lower level in a forced manner where the energy is returned to the input with dtrans low, needs to be weighed against the higher leakage power loss when the voltage drifts down with dtrans high. since the efficiency calculations require com- plex workload duty factors to be taken into considera- tion, a simple setting of the dtrans pin allows testing and comparison in both modes to determine which mode offers best efficiency. table 3 is the dtrans operating modes truth table. combined-mode operation combined mode (refin2 = v cc ) combined-mode operation allows the max8775 to sup- port even higher output currents by sharing the load current between two phases, distributing the power dissipation over several power components. the max8775 is configured in combined mode by connecting refin2 to v cc and ovp2 to ref or v cc . see figure 2 for the combined-mode standard application schematic. see the ovp2 connection requirements in the pin description table. phase transition (on2) while in combined mode, on1 functions as the master control signal that enables/disables the combined out- put. on2 enables/disables only phase 2. this allows for flexible power management where phase 2 can be dis- abled at lighter loads, operating at the most optimal point of the efficiency curve. the max8775 does not override the on2 signal during startup and shutdown. if on2 is low during startup and shutdown, the max8775 operates only in one phase. since the startup and shut- down slew rates are slow and the load currents are typi- cally low, one-phase operation during startup and shutdown might be possible. actual system testing and characterization of system load is required to guarantee operation in this mode. dual and combinable graphics core controller for notebook computers 20 ______________________________________________________________________________________ target pgood threshold fixed ov threshold refin refin transition (skip mode, downward transition disabled) mode refin(high) refin(low) 20 s 20 s pwm mode dh pulse skip pulse skip pgood output dragged down by load v out(high) v out(low) blank high-z blank high-z figure 9. refin transition (skip mode, downward transition disabled) dtrans skip_ operation during transition xh skip_ sets the respective phase in forced-pwm mode. all positive and negative refin transitions are forced. pgood_ is blanked during the slew_ capacitor transition + 20?. hl skip_ sets the respective phase in pulse-skipping mode. negative refin transitions are not forced, and the output voltage is discharged by the load. ll skip_ sets the respective phase in pulse-skipping mode. all positive and negative refin transitions are forced. pgood_ is blanked during the slew_ capacitor transition + 20?. table 3. dtrans operating modes truth table
while on2 is low, pgood2 is blanked high imped- ance. when on2 goes high again, the pgood2 cur- rent-balance comparator is reenabled. current balance (cci2) cci2 is the output of the current-balance transconduc- tance amplifier. the voltage level on cci2 allows fine adjustment to the duty cycle of phase 2, keeping phase 2? current in balance with phase 1. when v cci2 is 20% above or below v ref , pgood2 goes low, indicating the currents in the two phases are not balanced. place a 47pf capacitor from cci2 to agnd to integrate the current balance error. cci2 is clamped to ref when on2 is low. cci2 is unused in separate mode, and can be left unconnected. current-limit protection the current-limit circuit uses differential current-sense inputs (csh_ and csl_) to limit the peak inductor cur- rent. if the magnitude of the current-sense signal exceeds the current-limit threshold, the pwm controller turns off the high-side mosfet (figure 3). at the next rising edge of the internal oscillator, the pwm controller does not initiate a new cycle unless the current-sense signal drops below the current-limit threshold. the actual maximum load current is less than the peak cur- rent-limit threshold by an amount equal to half the inductor ripple current. therefore, the maximum load capability is a function of the current-sense resistance, inductor value, switching frequency, and duty cycle (v out /v in ). in forced-pwm mode, the max8775 also implements a negative current limit to prevent excessive reverse inductor currents when v out is sinking current. the negative current-limit threshold is set to approximately -120% of the positive current limit and tracks the posi- tive current limit. the current limit is fixed at 30mv (typ). mosfet gate drivers (dh_, dl_) the dh_ and dl_ drivers are optimized for driving moderate-sized high-side, and larger low-side power mosfets. this is consistent with the low duty factor seen in notebook applications, where a large v in - v out differential exists. the high-side gate drivers (dh_) source and sink 2a, and the low-side gate dri- vers (dl_) source 1.7a and sink 3.3a. this ensures robust gate drive for high-current applications. the dh_ floating high-side mosfet drivers are powered by charge pumps at bst_ while the dl_ synchronous-rec- tifier drivers are powered directly by the external 5v supply (v dd ). adaptive dead-time circuits monitor the dl_ and dh_ drivers and prevent either fet from turning on until the other is fully off. the adaptive driver dead time allows operation without shoot-through with a wide range of mosfets, minimizing delays and maintaining efficien- cy. there must be a low-resistance, low-inductance path from the dl_ and dh_ drivers to the mosfet gates for the adaptive dead-time circuits to work prop- erly; otherwise, the sense circuitry in the max8775 interprets the mosfet gates as ?ff?while charge actually remains. use very short, wide traces (50 mils to 100 mils wide if the mosfet is 1in from the driver). the internal pulldown transistor that drives dl_ low is robust, with a 0.6 (typ) on-resistance. this helps pre- vent dl_ from being pulled up due to capacitive cou- pling from the drain to the gate of the low-side mosfets when the inductor node (lx_) quickly switches from ground to v in . applications with high input voltages and long inductive driver traces may require additional gate- to-source capacitance to ensure fast-rising lx_ edges, do not pull up the low-side mosfets?gate, causing shoot-through currents. the capacitive coupling between lx_ and dl_ created by the mosfets?gate-to- drain capacitance (c rss ), gate-to-source capacitance (c iss - c rss ), and additional board parasitics should not exceed the following minimum threshold: lot-to-lot variation of the threshold voltage can cause problems in marginal designs. adding a resistor less than 10 in series with bst_ might remedy the problem by increasing the turn-on time of the high-side mosfet without degrading the turn-off time. power-good output (pgood_) pgood_ is the open-drain output of a comparator that continuously monitors each smps output voltage for overvoltage and undervoltage conditions. pgood_ is actively held low in shutdown (on_ = gnd), soft-start, and soft-shutdown. once the soft-start terminates, pgood_ becomes high impedance as long as the out- put does not drop below 150mv from the nominal regu- lation voltage set by refin_. pgood_ goes low once the output drops 150mv below its nominal regulation point, an output overvoltage fault occurs, or on_ is pulled low. for a logic-level pgood_ output voltage, connect an external pullup resistor between pgood_ and +5v or +3.3v. a 100k pullup resistor works well in most applications. pgood_ is blanked high impedance during all transi- tions detected at refin_ until 20? after the output reaches the regulation voltage. vv c c gs th in rss iss () > ? ? ? ? ? ? max8775 dual and combinable graphics core controller for notebook computers ______________________________________________________________________________________ 21
max8775 in combined mode (refin2 = v cc ), pgood1 indi- cates the output voltage is in regulation, while pgood2 indicates the currents between the two phases are in balance. pgood2 is the output of a comparator that monitors the voltage difference between cci2 and ref. since cci2 is the output of a transconductance amplifi- er, even small current imbalance over a long time caus- es cci2 to go high or low, depending on the current imbalance. whenever cci2 is 20% above or below ref (cci2 3v or cci2 2v), pgood2 goes low, indicat- ing the currents in the two phases are not balanced. pgood2 is blanked high impedance during all transi- tions detected at refin_ until 20? after the output reaches the regulation voltage. fault protection output overvoltage protection the max8775 includes an ovp_ pin that allows flexible setting of the overvoltage fault threshold. the overvolt- age threshold is 200mv (typ) above the voltage at the ovp_ pin. this simplifies the configuration, allowing the ovp_ pin to be directly connected to refin_, eliminating the need for extra resistors to set the overvoltage level. if the output voltage of either smps rises 200mv above its nominal regulation voltage, the corresponding con- troller sets its overvoltage fault latch, pulls pgood_ low, and forces dl_ high for the faulted side. the other controller is not affected. if the condition that caused the overvoltage persists (such as a shorted high-side mosfet), the battery fuse blows. cycle v cc below 1v or toggle both on_ pins to clear the overvoltage fault latch and restart the smps controller. in combined mode (refin2 = v cc ), ovp1 sets the overvoltage fault threshold for the combined output, while ovp2 is connected to ref when ovp is enabled, and to v cc when ovp is disabled. output undervoltage protection if the output voltage of either smps falls 300mv below its regulation voltage, the corresponding controller sets its undervoltage fault latch, pulls pgood_ low, and begins soft-shutdown for the faulted side by pulsing dl_. dh_ remains off during the soft-shutdown sequence initiated by an undervoltage fault. the other controller is not affected. after soft-shutdown has com- pleted, the max8775 forces dl_ high and dh_ low. cycle v cc below 1v or toggle on_ to clear the under- voltage fault latch and restart the smps controller. v cc por and uvlo power-on reset (por) occurs when v cc rises above approximately 2v, resetting the fault latch and prepar- ing the pwm for operation. v cc undervoltage-lockout (uvlo) circuitry inhibits switching, forces pgood_ low, and forces the dl_ gate drivers low. if v cc drops low enough to trip the uvlo comparator while on_ is high, the max8775 immediately forces dh_ and dl_ low on both controllers. the output dis- charges to 0v at a rate dependent on the load and the total output capacitance. this prevents negative output voltages, eliminating the need for a schottky diode to gnd at the output. dual and combinable graphics core controller for notebook computers 22 ______________________________________________________________________________________ mode condition description power-up v cc uvlo when on_ is high, dl_ is forced low as v cc falls below the 3.95v (typ) falling uvlo threshold. dl_ is forced high when v cc falls below 1v (typ). run on1 or on2 enabled normal operation. output overvoltage protection (ovp) either output > 200mv above nominal level when the overvoltage comparator trips, the faulted side sets the ov latch, forcing pgood_ low and dl_ high. an ov fault on one smps does not affect the operation of the other smps. the o v l atch i s cl ear ed b y cycl i ng v c c b el ow 1v or cycl i ng b oth o n _ p i ns. output undervoltage protection (uvp) either output < 300mv below nominal level, uvp is enabled 6144 clock cycles (1/f osc ) after the output is enabled (on_ going high) when the undervoltage comparator trips, the faulted side sets the uv latch, forcing pgood_ low and initiating the soft-shutdown sequence by pulsing only dl_. dl_ goes low after soft-shutdown. a uv fault on one smps does not affect the operation of the other smps. the u v l atch i s cl ear ed b y cycl i ng v c c b el ow 1v or cycl i ng the r esp ecti ve o n _ p i n. shutdown on1 and on2 are driven low dl_ stays low after soft-shutdown is completed. all circuitry is shut down. thermal shutdown t j > +160? exited by por or cycling on1 and on2. dl1 and dl2 remain low. table 4. operating modes truth table
thermal-fault protection the max8775 features a thermal-fault protection circuit. when the junction temperature rises above +160?, a thermal sensor sets the fault latches, pulls pgood_ low, and shuts down both smps controllers using the soft-shutdown sequence (see the soft-start and soft- shutdown section). cycle v cc below 1v or toggle on1 and on2 to clear the fault latches and restart the con- trollers after the junction temperature cools by 15?. design procedure firmly establish the input voltage range and maximum load current before choosing a switching frequency and inductor operating point (ripple-current ratio). the primary design trade-off lies in choosing a good switch- ing frequency and inductor operating point, and the fol- lowing four factors dictate the rest of the design: input voltage range. the maximum value (v in(max) ) must accommodate the worst-case, high ac-adapter voltage. the minimum value (v in(min) ) must account for the lowest battery voltage after drops due to connectors, fuses, and battery selector switches. if there is a choice at all, lower input volt- ages result in better efficiency. maximum load current. there are two values to consider. the peak load current (i load(max) ) determines the instantaneous component stresses and filtering requirements and thus drives output capacitor selection, inductor saturation rating, and the design of the current-limit circuit. the continu- ous load current (i load ) determines the thermal stresses and thus drives the selection of input capacitors, mosfets, and other critical heat-con- tributing components. switching frequency. this choice determines the basic trade-off between size and efficiency. the optimal frequency is largely a function of maximum input voltage, due to mosfet switching losses that are proportional to frequency and v in 2 . the opti- mum frequency is also a moving target, due to rapid improvements in mosfet technology that are making higher frequencies more practical. inductor operating point. this choice provides trade-offs between size and efficiency and between transient response and output ripple. low inductor values provide better transient response and small- er physical size, but also result in lower efficiency and higher output ripple due to increased ripple currents. the minimum practical inductor value is one that causes the circuit to operate at the edge of critical conduction (where the inductor current just touches zero with every cycle at maximum load). inductor values lower than this grant no further size- reduction benefit. the optimum operating point is usually found between 20% and 30% ripple current. when pulse skipping ( skip_ low and light loads), the inductor value also determines the load-current value at which pfm/pwm switchover occurs. inductor selection the per-phase switching frequency and inductor oper- ating point determine the inductor value as follows: for example: i load(max) = 15a, v in = 12v, v out = 1.5v, f osc = 300khz, 30% ripple current or lir = 0.3: find a low-loss inductor having the lowest possible dc resistance that fits in the allotted dimensions. for the selected inductance value, the actual peak-to-peak inductor ripple current ( i inductor ) is defined by: ferrite cores are often the best choice, although pow- dered iron is inexpensive and can work well at 200khz. the core must be large enough not to saturate at the peak inductor current (i peak ): transient response the inductor ripple current also impacts transient- response performance, especially at low v in - v out dif- ferentials. low inductor values allow the inductor current to slew faster, replenishing charge removed from the output filter capacitors by a sudden load step. the total output voltage sag is the sum of the voltage sag while the inductor is ramping up, and the voltage sag before the next pulse can occur: where d max is the maximum duty factor (see the electrical characteristics ), t is the switching period (1 / f osc ), and t equals v out / v in x t when in pwm mode, or l x 0.2 x i max / (v in - v out ) when in skip v li cvd v itt c sag load max out in max out load max out = () ? () + ? () ? () () 2 2 ii i peak load max inductor =+ () 2 i vvv vf l inductor out in out in osc = ? () l vvv v khz a h = ? () = 18 12 18 12 300 15 0 3 097 .. . . l vvv v f i lir out in out in osc load max = ? () () max8775 dual and combinable graphics core controller for notebook computers ______________________________________________________________________________________ 23
max8775 mode. the amount of overshoot during a full-load to no- load transient due to stored inductor energy can be cal- culated as: where n ph is 2 in combined mode when both phases are active. setting the current limit the minimum current-limit threshold must be great enough to support the maximum load current when the current limit is at the minimum tolerance value. the per- phase peak inductor current occurs at i load(max) plus half the ripple current; therefore: where n ph is 2 in combined mode, and i limit equals the minimum current-limit threshold voltage divided by the current-sense resistance (r sense_ ). for the 30mv default setting, the minimum current-limit threshold is 26mv. the current-sense method (figure 10) and magnitude determine the achievable current-limit accuracy and power loss. the sense resistor can be determined by: r sense_ = v lim_ / i limit_ for the best current-sense accuracy and overcurrent protection, use a 1% tolerance current-sense resistor between the inductor and output as shown in figure 10a. this configuration constantly monitors the inductor cur- rent, allowing accurate current-limit protection. however, the parasitic inductance of the current-sense resistor can cause current-limit inaccuracies, especially when using low-value inductors and current-sense resistors. this parasitic inductance (l esl ) can be cancelled by adding an rc circuit across the sense resistor with an equivalent time constant: alternatively, low-cost applications that do not require highly accurate current-limit protection may reduce the overall power dissipation by connecting a series rc circuit across the inductor (figure 10b) with an equiva- lent time constant: cr l r eq eq esl sense = i i n i limit load max ph inductor >+ ? ? ? ? ? ? () 2 v il nc v soar load max ph out out () () 2 2 dual and combinable graphics core controller for notebook computers 24 ______________________________________________________________________________________ sense resistor l max8775 c out input (v in ) c in csl_ csh_ pgnd dl_ dh_ lx_ c eq r eq n h n l d l l esl r sense c eq r eq = l esl r sense max8775 c out input (v in ) c in b) lossless inductor sensing csl_ csh_ pgnd dl_ dh_ lx_ c eq r 1 r 2 n h n l d l l inductor a) output series resistor sensing r dcr r cs = r2 = r dcr r1 + r2 r dcr = l [ 1 + 1 ] c eq r1 r2 figure 10. current-sense configurations
and: where r cs is the required current-sense resistance, and r dcr is the inductor? series dc resistance. use the worst-case inductance and r dcr values provided by the inductor manufacturer, adding some margin for the inductance drop over temperature and load. output capacitor selection the output filter capacitor must have low enough equiva- lent series resistance (esr) to meet output ripple and load-transient requirements, yet have high enough esr to satisfy stability requirements. the output capacitance must be high enough to absorb the inductor energy while transitioning from full-load to no-load conditions without tripping the overvoltage fault protection. when using high-capacitance, low-esr capacitors (see stabili- ty requirements), the filter capacitor? esr dominates the output voltage ripple. therefore, the output capacitor? size depends on the maximum esr required to meet the output voltage ripple (v ripple(p-p) ) specifications: in idle mode, the inductor current becomes discontinuous, with peak currents set by the idle mode current-sense threshold (v idle = 0.2v limit ). in idle mode, the no-load output ripple can be determined as follows: the actual capacitance value required relates to the physical size needed to achieve low esr, as well as to the chemistry of the capacitor technology. thus, the capacitor is usually selected by esr and voltage rating rather than by capacitance value (this is true of tanta- lums, os-cons, polymers, and other electrolytics). when using low-capacity filter capacitors, such as ceramic capacitors, size is usually determined by the capacity needed to prevent v sag and v soar from causing problems during load transients. generally, once enough capacitance is added to meet the over- shoot requirement, undershoot at the rising load edge is no longer a problem (see the v sag and v soar equa- tions in the transient response section). however, low- capacity filter capacitors typically have high esr zeros that may affect the overall stability (see the output capacitor stability considerations section). output capacitor stability considerations stability is determined by the value of the output zero relative to the switching frequency. the boundary of instability is given by the following equation: where: for a typical 300khz application, the output zero fre- quency must be well below 95khz, preferably below 50khz. tantalum and os-con capacitors in wide- spread use at the time of publication have typical esr zero frequencies of 25khz. in the design example used for inductor selection, the esr needed to support 25mv p-p ripple is 25mv/1.5a = 16.7m . one 330?/2.5v sanyo polymer (tpe) capacitor provides 7m (max) esr. together with the 1.5m current- sense resistors, the output zero is 25khz, zero is 25khz, well within the bounds of stability. the max8775 is optimized for low-duty-cycle opera- tions. steady-state operation at 45% duty cycle or higher is not recommended. the easiest method for checking stability is to apply a very fast zero-to-max load transient and carefully observe the output voltage ripple envelope for over- shoot and ringing. it can help to simultaneously monitor the inductor current with an ac current probe. do not allow more than one cycle of ringing after the initial step-response under/overshoot. input capacitor selection the input capacitor must meet the rms ripple current requirement (i rms ) imposed by the switching currents. for a single step-down converter, the rms input ripple current is defined by the output load current (i out ), input voltage, and output voltage, with the worst-case condition occurring at v in = 2v out : for a dual +180 interleaved controller, the out-of- phase operation reduces the rms input ripple current, effectively lowering the input capacitance require- ments. when both outputs operate with a duty cycle less than 50% (v in > 2v out ), the rms input ripple cur- rent is defined by the following equation: i v v ii i v v ii i rms out in out out in out in out out in = ? ? ? ? ? ? ? () + ? ? ? ? ? ? ? () 1 11 2 22 ii vvv v rms out out in out in = ? () f rrc esr esr sense out = + 1 24 () r r and f f esr sense esr sw < 2 v vr r ripple p p idle esr sense () ? = v r i lir ripple p p esr load max () ( ) ? = r l crr dcr eq =+ ? ? ? ? ? ? 1 1 1 2 r r rr r cs dcr = + 2 12 max8775 dual and combinable graphics core controller for notebook computers ______________________________________________________________________________________ 25
max8775 where i in is the average input current: in combined mode (refin2 = v cc ) with both phases active, the input rms current simplifies to: for most applications, nontantalum chemistries (ceram- ic, aluminum, or os-con) are preferred due to their resistance to power-up surge currents typical of sys- tems with a mechanical switch or connector in series with the input. choose a capacitor that has less than 10? temperature rise at the rms input current for opti- mal reliability and lifetime. power-mosfet selection most of the following mosfet guidelines focus on the challenge of obtaining high load-current capability when using high-voltage (> 20v) ac adapters. low- current applications usually require less attention. the high-side mosfet (n h ) must be able to dissipate the resistive losses plus the switching losses at both v in(min) and v in(max) . ideally, the losses at v in(min) should be roughly equal to the losses at v in(max) , with lower losses in between. if the losses at v in(min) are significantly higher, consider increasing the size of n h . conversely, if the losses at v in(max) are significantly higher, consider reducing the size of n h . if v in does not vary over a wide range, optimum efficiency is achieved by selecting a high-side mosfet (n h ) that has conduction losses equal to the switching losses. choose a low-side mosfet (n l ) that has the lowest possible on-resistance (r ds(on) ), comes in a moderate- sized package (i.e., 8-pin so, dpak, or d 2 pak), and is reasonably priced. ensure that the max8775 dl_ gate driver can supply sufficient current to support the gate charge and the current injected into the parasitic drain- to-gate capacitor caused by the high-side mosfet turning on; otherwise, cross-conduction problems can occur. switching losses are not an issue for the low-side mosfet since it is a zero-voltage switched device when used in the step-down topology. power-mosfet dissipation worst-case conduction losses occur at the duty factor extremes. for the high-side mosfet (n h ), the worst- case power dissipation due to resistance occurs at minimum input voltage: pd (n h resistive) = generally, use a small high-side mosfet to reduce switching losses at high input voltages. however, the r ds(on) required to stay within package power-dissi- pation limits often limits how small the mosfet can be. the optimum occurs when the switching losses equal the conduction (r ds(on) ) losses. high-side switching losses do not become an issue until the input is greater than approximately 15v. calculating the power dissipation in high-side mosfets (n h ) due to switching losses is difficult, since it must allow for difficult-to-quantify factors that influence the turn-on and turn-off times. these factors include the internal gate resistance, gate charge, threshold voltage, source inductance, and pcb layout characteristics. the following switching loss calculation provides only a very rough estimate and is no substitute for breadboard evaluation, preferably including verification using a ther- mocouple mounted on n h : pd (n h switching) = where c rss is the reverse transfer capacitance of n h , and i gate is the peak gate-drive source/sink current (1a typ). switching losses in the high-side mosfet can become a heat problem when maximum ac adapter voltages are applied, due to the squared term in the switching- loss equation (c x v in 2 x f sw ). if the high-side mosfet chosen for adequate r ds(on) at low battery voltages becomes extraordinarily hot when subjected to v in(max) , consider choosing another mosfet with lower parasitic capacitance. for the low-side mosfet (n l ), the worst-case power dissipation always occurs at maximum battery voltage: pd (n l resistive) = the absolute worst case for mosfet power dissipation occurs under heavy overload conditions that are greater than i load(max) , but are not high enough to exceed the current limit and cause the fault latch to trip. to protect against this possibility, ?verdesign?the cir- cuit to tolerate: 1 2 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? () v v ir out in max load ds on () () () () () vif i q i cv f in max load sw gate gsw gate oss in max sw ? ? ? ? ? ? ? ? ? ? ? ? + 2 2 v v ir out in load ds on ? ? ? ? ? ? () 2 () ii v v v v rms out out in out in = ? ? ? ? ? ? ? ? ? ? ? ? ? 1 2 i v v i v v i in out in out out in out = ? ? ? ? ? ? + ? ? ? ? ? ? 1 1 2 2 dual and combinable graphics core controller for notebook computers 26 ______________________________________________________________________________________
where i limit is the peak current allowed by the current- limit circuit, including threshold tolerance and sense- resistance variation. the mosfets must have a relatively large heatsink to handle the overload power dissipation. choose a schottky diode (d l ) with a forward voltage drop low enough to prevent the low-side mosfet? body diode from turning on during the dead time. boost capacitors the boost capacitors (c bst ) must be selected large enough to handle the gate charging requirements of the high-side mosfets. typically, 0.1? ceramic capacitors work well for low-power applications driving medium-sized mosfets. however, high-current appli- cations driving large, high-side mosfets require boost capacitors larger than 0.1?. for these applications, select the boost capacitors to avoid discharging the capacitor more than 200mv while charging the high- side mosfets?gates: where q gate is the total gate charge specified in the high-side mosfets?data sheet. for example, assume the si7634dp n-channel mosfet is used on the high side. according to the manufacturer? data sheet, a sin- gle si7634dp has a gate charge of 21nc (v gs = 5v). using the above equation, the required boost capaci- tance would be: selecting the closest standard value, this example requires a 0.1? ceramic capacitor. applications information duty-cycle limits minimum input voltage the minimum input operating voltage (dropout voltage) is restricted by the maximum duty-cycle specification (see the electrical characteristics table). however, keep in mind that the transient performance gets worse as the step-down regulators approach the dropout volt- age, so bulk output capacitance must be added (see the voltage sag and soar equations in the design procedure section). the absolute point of dropout occurs when the inductor current ramps down during the off-time ( i down ) as much as it ramps up during the on-time ( i up ). this results in a minimum operating voltage defined by the following equation: where v chg and v dis are the parasitic voltage drops in the charge and discharge paths, respectively. a rea- sonable minimum value for h is 1.5, while the absolute minimum input voltage is calculated with h = 1. maximum input voltage the max8775 controller includes a minimum on-time specification, which determines the maximum input operating voltage that maintains the selected switching frequency (see the electrical characteristics table). operation above this maximum input voltage results in pulse-skipping operation, regardless of the operating mode selected by skip_ . at the beginning of each cycle, if the output voltage is still above the feedback threshold voltage, the controller does not trigger an on- time pulse, effectively skipping a cycle. this allows the controller to maintain regulation above the maximum input voltage, but forces the controller to effectively operate with a lower switching frequency. this results in an input threshold voltage at which the controller begins to skip pulses (v in(skip) ): where f osc is the switching frequency selected by osc. pcb layout guidelines careful pcb layout is critical to achieving low switching losses and clean, stable operation. the switching power stage requires particular attention (figure 11). if possible, mount all the power components on the top side of the board, with their ground terminals flush against one another. follow these guidelines for good pcb layout: keep the high-current paths short, especially at the ground terminals. this practice is essential for sta- ble, jitter-free operation. keep the power traces and load connections short. this practice is essential for high efficiency. using thick copper pcb (2oz vs. 1oz) can enhance full- load efficiency by 1% or more. correctly routing pcb traces is a difficult task that must be approached in terms of fractions of centimeters, vv ft in skip out osc on min () () = ? ? ? ? ? ? 1 vvvh d vv in min out chg max out dis () =++ ? ? ? ? ? ? ? + () 1 1 c nc mv f bst == 13 200 0 105 . c q mv bst gate = 200 ii i load limit inductor =? ? ? ? ? ? ? 2 max8775 dual and combinable graphics core controller for notebook computers ______________________________________________________________________________________ 27
max8775 where a single m of excess trace resistance caus- es a measurable efficiency penalty. minimize current-sensing errors by connecting csh_ and csl_ directly across the current-sense resistor (r sense_ ). when trade-offs in trace lengths must be made, it is preferable to allow the inductor charging path to be made longer than the discharge path. for example, it is better to allow some extra distance between the input capacitors and the high-side mosfet than to allow distance between the inductor and the low- side mosfet or between the inductor and the out- put filter capacitor. route high-speed switching nodes (bst_, lx_, dh_, and dl_) away from sensitive analog areas (ref, refin_, csh_, csl_). layout procedure 1) place the power components first, with ground ter- minals adjacent (n l _ source, c in , c out _, and d l _ anode). if possible, make all these connections on the top layer with wide, copper-filled areas. 2) mount the controller ic adjacent to the low-side mosfet, preferably on the back side opposite n l_ and n h_ to keep lx_, gnd, dh_, and the dl_ gate- drive lines short and wide. the dl_ and dh_ gate traces must be short and wide (50 mils to 100 mils wide if the mosfet is 1in from the controller ic) to keep the driver impedance low and for proper adaptive dead-time sensing. 3) group the gate-drive components (bst_ capacitor, v dd bypass capacitor) together near the controller ic. 4) make the dc-dc controller ground connections as shown in figures 1, 2, and 11. this diagram can be viewed as having two separate ground planes: power ground, where all the high-power compo- nents go; and an analog ground plane for sensitive analog components. the analog ground plane and power ground plane must meet only at a single point directly at the ic. 5) connect the output power planes directly to the out- put filter capacitor positive and negative terminals with multiple vias. place the entire dc-dc converter circuit as close to the load as is practical. dual and combinable graphics core controller for notebook computers 28 ______________________________________________________________________________________
max8775 dual and combinable graphics core controller for notebook computers ______________________________________________________________________________________ 29 output 2 phase 1 c out c out c out c out c in c in phase 2 output 1 kelvin sense vias under the sense resistor (see evaluation kit) kelvin sense vias under the sense resistor (see evaluation kit) via to power ground ref bypass capacitor connect gnd and pgnd the controller at one point only as shown connect the exposed pad to analog gnd v cc bypass capacitor via to analog ground inductor inductor r sense r sense input power ground figure 11. pcb layout chip information transistor count: 6372 process: bicmos
max8775 dual and combinable graphics core controller for notebook computers maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 30 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2006 maxim integrated products is a registered trademark of maxim integrated products. inc. package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .) qfn thin.eps
e nglish ? ???? ? ??? ? ??? what's ne w p roducts solutions de sign ap p note s sup p ort buy comp any me mbe rs max8775 part number table notes: see the max8775 quickview data sheet for further information on this product family or download the max8775 full data sheet (pdf, 1.0mb). 1. other options and links for purchasing parts are listed at: http://www.maxim-ic.com/sales . 2. didn't find what you need? ask our applications engineers. expert assistance in finding parts, usually within one business day. 3. part number suffixes: t or t&r = tape and reel; + = rohs/lead-free; # = rohs/lead-exempt. more: see full data sheet or part naming c onventions . 4. * some packages have variations, listed on the drawing. "pkgc ode/variation" tells which variation the product uses. 5. part number free sample buy direct package: type pins size drawing code/var * temp rohs/lead-free? materials analysis max8775etj+ thin qfn;32 pin;5x5x0.8mm dwg: 21-0140k (pdf) use pkgcode/variation: t3255+5 * -40c to +85c rohs/lead-free: yes materials analysis max8775etj+t thin qfn;32 pin;5x5x0.8mm dwg: 21-0140k (pdf) use pkgcode/variation: t3255+5 * -40c to +85c rohs/lead-free: yes materials analysis didn't find what you need? c ontac t us: send us an email c opyright 2 0 0 7 by m axim i ntegrated p roduc ts , dallas semic onduc tor ? legal n otic es ? p rivac y p olic y

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